Leader in TimingProgrammable options and customization capabilities address unique customer requirements |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Lowest jitter and lowest power features set Renesas apart from the competition. With a product portfolio 10 times greater and broader than any other, Renesas is the world’s leader in silicon timing and is in a unique position to address the needs of virtually any application. With the industry’s largest market share, Renesas is the only one-stop-shop for timing, offering products from full-featured system solutions to simple clock building-block devices. Factory-programmable options and clock solution customization capabilities address unique customer requirements, while the lowest jitter and lowest power features set Renesas apart from the competition. Products are accompanied by a world-class support team driven by service and responsiveness goals. To learn more, simply scroll down or use the Product Blocks to jump ahead. Clock DistributionZero Delay BuffersRenesas’ family of zero delay buffers provides low jitter and low input to output delay for high-speed clock distribution applications. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback path eliminates the delay through other devices and can be on-chip or external. On-chip feedback is obtained from the CLKOUT pad. Some parts have the option to add multiplier or divider paths to the outputs. Renesas’ zero delay buffer family includes products supporting supply voltages from 2.5 V to 5 V, output frequencies 5 to 210 MHz, and 1 to 9 outputs. Typical output types supported are CMOS and TTL. Zero Delay buffers; which are ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. 
Fan-Out BuffersRenesas’ family of fan-out buffers provides multiple low skew copies of the reference input. The large fan-out from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Renesas’ fan-out buffer family includes products supporting supply voltages from 1.2 V up to 5 V, output frequencies from 0 to 200 MHz, and 1 to 16 outputs. Typical output types supported are CMOS, TTL, and LVCMOS. Fan-out buffers are ideal for clock and signal distribution in a large variety of systems, from personal computers to consumer electronics or industrial systems.
5P1103 / 5P1105 Programmable Universal Output Buffers
View 5P1103 and 5P1105 IC Clock Generators Programmable Fan-out Buffer Product Brief
Clock GenerationVersaClock® 5 with Additional PCIe Outputs
The 5P49V5907 and 5P49V5908 devices have three outputs that can generate any frequency up to 350 MHz in configurable output types – LVPECL, LVDS, HCSL or LVCMOS, and additional four or eight LP-HCSL outputs specifically for PCIe clocking. They possess the same best-in-class jitter and power performance as the original 5P49V5901 device. VersaClock 5 programmable timing devices feature excellent jitter performance at half the power of competing devices. With RMS phase jitter of less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range, the products are ideal for such markets as high-end consumer, networking, computing, industrial and communications. Features
Applications
View All VersaClock 5 5P49V5907 and 5P49V5908 5P49V5907 Datasheet | 5P49V5908 Datasheet
VersaClock® 5 Programmable Clocks with Integrated Crystal
Features
VersaClock® 5 Low-Power Programmable Clock GeneratorThe Renesas5P49V5901 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with universal outputs capable of generating any output frequency. Renesas5P49V5901 is intended for high-performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface. This is Renesas’ fifth generation of programmable clock technology (VersaClock 5).The frequencies are generated from a single reference clock or crystal input. A glitchless manual switchover function allows one of the redundant clock inputs to be selected during normal operation. Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I²C addresses to allow multiple devices to be used in a system.
Universal Frequency Translator Devices
View All UFT Devices | FemtoClock NG UFT Product Brief
VersaClock® IIIVersaClock products allow designers to save board space and cost by replacing crystals, oscillators and buffers with a single timing device. Exceptional versatility and configurability allow for maximum freedom in the design process. There are four internal PLLs, each individually programmable, allowing for up to seven unique frequencies. These frequencies are generated from a single reference clock, which can come from one of two redundant clock inputs. A glitchless automatic or manual switchover function allows the redundant clock to be selected during normal operation.
FemtoClock Next Generation (NG) SynthesizersRenesas FemtoClock® NG Universal Frequency Translators (UFT™) cover all your frequency synthesis and translation needs. Family members are available that support 1, 2, 3 or 4 PLLs in a single package. As a frequency synthesizer, a low-cost, readily-available fundamental mode crystal can be used to generate output frequencies that range from 1 MHz to 1.3 GHz. The internal architecture of the device allows any frequency of crystal from 16 MHz to 40 MHz to be used regardless of the frequency desired. As a frequency translator, this family of devices accepts 1 or 2 input reference clocks per PLL from 8 kHz to 710 MHz; switching between them as necessary and generates any output frequency from 1 MHz to 1.3 GHz with no frequency translation error in most cases. Family members support either one or two different pin-selectable configurations per PLL that may be pre-loaded into the internal One-Time Programmable (OTP) non-volatile memory for automatic operation directly from power-up, or an I²C serial interface can be used to set the desired configurations. View All FemtoClock NG Synthesizers Products | Crystal Timing Budget Application Note
High-Performance Crystal OscillatorsXO - Crystal Oscillators
High-Performance Crystal Oscillators Product Brief
Jitter Attenuators with Frequency Translation
View All Jitter Attenuator Products
PCI ExpressPCIe Gen1-2-3 Clock GeneratorsThe 6 and 8 output 3.3 V clock generators 9FGL06 and 9FGL08 join the existing 1.5 V and 1.8 V families offering their low-power PCI Express® (PCIe) portfolio of clock generators. The new products operate at approximately 100 milliwatts, making them the lowest power 3.3 V PCIe clock generators on the market. By operating at roughly one-fifth the power of traditional PCIe clock devices, the Renesas 3.3 V devices effectively eliminate thermal concerns. With their integrated terminations, the 9FGL06 and 9FGL08 devices’ ultra-compact 5 x 5 and 6 x 6 mm packages can deliver up to a 90 percent reduction in board area. Factory programmable versions provide quick-turn device optimizations to meet exact customer requirements. The SoC-friendly devices greatly exceed the phase jitter requirements of the PCIe Gen3 specification in anticipation of the upcoming PCIe Gen4 specification, and are also suitable for applications needing less than 3ps rms 12k-20M phase jitter, such as gigabit Ethernet and other high-performance applications. The 3.3 V devices are pin-compatible to Renesas’ highly successful 1.5 V 9FGU-series and 1.8 V 9FGV-series PCIe clock generators. The timing family targets power- and space-constrained designs in both consumer and high-performance applications, providing enterprise-level performance while lowering the total cost of ownership. The entire family is compliant with PCIe generations 1, 2 and 3. The 3.3 V (L-series) family offers industry firsts that include:
Applications:
View All PCIe Gen1-2-3 Clock Generators | PCI Express Solutions Product Brief 9FGL06 Datasheet | 9FGL08 Datasheet
PCI Express® Clock Buffers
RF & JESD204B Timing8V97051 Wideband RF Synthesizer
The device features an integrated VCO with a large tuning range capable of providing multiband LO frequency synthesis, limiting the need for multiple narrow band RF synthesizers.
View All RF & JESD204B Timing Products | 8V97051 RF Synthesizer Product Brief | Datasheet Evaluation Board User Guide | 8V970xx LBW Calculator | IBIS Model Download Timing Commander Personality File
Complimentary Clock Tree Design and Review ServicesClock tree design can be a complex task with many considerations that are often overwhelming to designers unfamiliar with clock trees and the associated “language” of timing. While clock tree tools and wizards sometimes exist to assist with simple clock tree designs, these often fall short in real-world applications; automated tools simply cannot address many of the complexities of advanced requirements like phase jitter and spread spectrum. 
ResourcesScheme-It Design StartersProject: Increasing Outputs from a Clock Source using Low Jitter LVDS fan-out Buffer 
Project: VersaClock® 5 - 5P49V5901 Programmer Board 
Project: EVK-UFT285-6-7 Evaluation Board 
Product Training Modules
Videos
|
Renesas Electronics Corporation Videos 
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
 |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
The 5P1103 and 5P1105 are programmable universal fan-out buffers with universal outputs intended for high-performance consumer, networking, industrial, computing, and data communications applications. Configurations can be stored in on-chip one-time programmable (OTP) memory or changed using an I²C interface. The memory in the devices can be programmed or ordered with factory-programmed specifications.
Renesas announced the expansion of the VersaClock® 5 family of programmable clock generators with new devices that simplify the creation of PCI Express® clocks while providing the flexible outputs for which VersaClock 5 is known. The new members of the high-performance VersaClock 5 family feature dedicated low-power HCSL (LP-HCSL) outputs that reduce board space and bill of materials (BOM) by providing an integrated clock generation and distribution solution for PCIe designs.
Renesas’ Universal Frequency Translator family of programmable clock generators is optimized for high-performance optical networks, 100 Gigabit Ethernet (GbE) interface applications, and wireless base stations. These devices are the single-chip programmable clock generators capable of generating eight different output frequencies with less than 300 femtoseconds RMS phase jitter over the standard 12 kHz to 20 MHz integration range. The 3rd generation UFT family of programmable clock generators offers eight independently programmable clock outputs with the flexibility to apply virtually any input frequency and select virtually any output frequency.
Renesas’ crystal oscillators offer designers a reliable and economical timing solution. Data throughput needs continue to rise for serial IO technologies. As these speeds increase, jitter requirements have become more stringent. Renesas’ new family of Crystal Oscillators, Renesas XO, is the response to the industry’s needs for high performance, low jitter clock sources. Renesas XO feature a typical jitter value of 300 fs RMS with a maximum value of 400 fs, integrated over 12 kHz to 20 MHz. Renesas offers the most precise timing solutions available with industry-leading accuracy over temperature, frequency stability, and best phase noise and jitter feature sets.
Problem solving solutions permit easy addition of functionality to existing systems, minimizing design time and cost. Renesas jitter attenuators use special purpose PLL to reconstruct PCI Express clocks, reducing inherent jitter. In some PCIe systems, the PCIe clocks are generated from a relatively high phase noise PLL frequency synthesizer. In these systems, a jitter attenuating device may be necessary to reduce high-frequency random and deterministic jitter components from the clock synthesizer and the system board.
PCI Express (PCIe) is globally recognized as the general purpose I/O that unifies the component interconnect across many applications including desktop computing, servers, workstations, storage, networking, enterprise routers, industrial test and control equipment, aerospace, and many more. Renesas is the only vendor to provide all the major building blocks for PCIe, including switches, bridges, signal integrity products for increasing channel length, and timing devices.
The 8V97051 wideband RF synthesizer/PLL with integrated VCO offers a combination of high performance, low power consumption and wide tuning range. 
