DDR4 DRAM Components

Kingston Technology's DRAM components are designed to meet the needs of embedded devices and are available with low-voltage variants for reduced power consumption. Kingston DDR4 components are offered in an operating case temperature range of 0°C to +95°C for commercial temperature and -40°C to +95°C for industrial temperature. Package options are available in 78-ball FBGA and 96-ball FBGA and are also lead-free and halogen-free. Kingston's DDR4 components offer data rates of 3200 Mbps and 2666 Mbps.

Features

• Double-data-rate architecture: two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bidirectional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
• Differential clock inputs (CK_t and CK_c)
• DLL aligns DQ and DQS transitions with CK transitions
• Data mask (DM) writes data-in at both the rising and falling edges of the data strobe
• Write cycle redundancy code (CRC) is supported
• Programmable preamble for read and write is supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on-the-fly
• Driver strength selected by MRS
• Dynamic on-die termination supported
• Two termination states such as RTT_PARK and RTT_NOM switchable by ODT pin
• Asynchronous RESET pin supported
• ZQ calibration supported
• Write levelization supported
• In compliance with the RoHS directive
• Internal V_REF DQ level generation is available
• Temperature-controlled auto refresh (TCAR) mode is supported
• Low-power auto self-refresh (LP ASR) mode is supported
• Command address (CA) parity (command/address) mode is supported
• Per DRAM addressability (PDA)
• Fine granularity refresh is supported
• Geardown mode (1/2 rate and 1/4 rate) is supported
• Self-refresh abort is supported
• Maximum power-saving mode is supported
• Banks grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
• DMI pin support for write data masking and DBIdc functionality