Each FPGA has a number of phase locked loops, or PLLs, for use in a design. The PLLs are a way to create alternate clock frequencies based on input frequencies. The frequencies are defined by the setting of N, M, O, and C parameters as shown here. The customer can also use the PLL to synchronize clocks and to also generate clocks with different phase relationships. The Efinity^® tool has a PLL wizard to help automate the setting needed to reach a desired frequency.