Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Slide 34
Slide 35
Slide 36
Slide 37
Product List
Here is the same RX CPU core that was just discussed along with its 64-bit instruction interface and its 32-bit data interface. Discussed earlier was the “Enhanced” Harvard architecture; here is where it happens: in this bus matrix. The matrix allows either instructions or data to be accessed through any one of three different paths.
PTM Published on: 2012-05-15
