The soft stop function allows the designer to bring the outputs down in a controlled manner, avoiding reverse biasing FPGA core and I/O voltages. As with soft start, soft-off is closed loop control to it's final programmed value. It can be programmed from 0.9V to 0.1V.  When the ramp reached the final value, both MOSFETs turn off. Shut down delays are also controllable as shown in the left hand picture.