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Product List
In addition to the pre-emphasis and equalization settings for debugging, the transceivers support dynamic partial reconfiguration of the transceiver I/Os which allows the user to change the payload size, initial link widths, and modify other parameters without reconfiguring the entire FPGA. During this partial reconfiguration, the PCIe core is held in reset. Additionally, ACJTAG is also available to debug connectivity issues.
PTM Published on: 2012-05-29
