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Product List
The PLLs in the Cyclone® IV FPGAs have four different operational modes. Source synchronous mode provides a clock-to-data relationship at the input pin (setup/hold), maintained at the IOE register. The no compensation mode is used to maintain the best jitter performance. Normal mode fully compensates the input clock delay for alignment with the clock at the IOE or core register. Lastly, the zero delay buffer mode ensures that the input clock is aligned with the dedicated external clock output.
PTM Published on: 2012-05-29
