Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Product List
Associated Content
There are dedicated pins for LVDS inputs and LVDS outputs for source synchronous buses. The LVDS pins support speeds up to 800 Mbps and gearing logic is included to simplify interfacing to the FPGA fabric for receive and transmit. Lastly, on-die terminations are included to negate the need for external resistors and simplify the layout.
PTM Published on: 2020-03-11
